The present invention relates to a test apparatus such as an LSI tester, and in particular to a test apparatus that stores a decision result of a level of a response signal from a device to be tested.
As the speed of devices to be tested such as LSIs becomes high, tests conducted in LSI testers become high in speed and accuracy. Therefore, it is necessary to apply a test signal to a device to be tested at high speed and effect a decision on a response signal from the device to be tested at high speed and at high accuracy. On the other hand, LSI testers are demanded to have reduced power consumption with due regard to environmental problems and have a larger number of pins in order to reduce the test cost. As a method for constructing a tester that satisfies these demands, it is promising to form the timing system in the tester of CMOS transistors.
FIG. 9 is a block diagram showing one configuration example of LSI testers. Reference numeral 1 denotes a logical value storage circuit, 2a and 2b analog comparators, 3 an LSI to be tested, 41 a timing generation circuit, 42 a pattern generation circuit, 43 a test signal signal generation circuit, 44 a driver, and 5 an expected value comparison circuit.
With reference to FIG. 9, the pattern generation circuit 42 generates predetermined waveform data for testing the LSI 3 to be tested serving as a device to be tested, and supplies the waveform data to the test waveform generation circuit 43. The test waveform generation circuit 43 generates a test waveform of the LSI 3 to be tested on the basis of the waveform data at timing of a waveform switchover edge (pulse) generated by the timing generation circuit 41, and supplies the test waveform to the LSI 3 to be tested via the driver 44. The waveform switchover edge has a period equivalent to a minimum period of the waveform data. In the LSI 3 to be tested, a predetermined test is conducted on the basis of the test waveform, and a response signal REP is output as a result of the test.
The response signal REP is supplied to the analog comparators 2a and 2b, and compared in level with predetermined thresholds ViH and ViL, respectively, therein. As shown in FIG. 10, the response signal REP is a signal that is 5 V at its H (High) level and 0 V at its L (Low) level. The thresholds ViH and ViL are set equal to, for example, 3 V and 1 V, respectively.
As shown in FIG. 10, the analog comparator 2a outputs a two-valued signal HCMP, which assumes the H level if the response signal REP is at least the threshold ViH and which assumes the L level otherwise. As shown in FIG. 10, the analog comparator 2b outputs a two-valued signal LCMP, which assumes the H level if the response signal REP is less than the threshold ViL and which assumes the L level otherwise. The two-valued signals HCMP and LCMP are supplied to the logical value storage circuit 1.
In the logical value storage circuit 1, logical values (H, L) of the two-valued signals HCMP and LCMP are detected at timing of decision edges (pulses) EH and EL generated by the timing generation circuit 41, and stored. As shown in FIG. 11, the logical value storage circuit 1 in the conventional art includes a D-type FF (flip-flop circuit) la for storing the logical value of the two-valued signal HCMP by using the decision edge EH for HCMP as a clock, and a D-type FF 1b for storing the logical value of the two-valued signal LCMP by using the decision edge EL for LCMP as a clock. The logical value of the two-valued signal HCMP is sampled at timing of the decision edge EH and stored in the FF 1a. The logical value of the two-valued signal LCMP is sampled at timing of the decision edge EL and stored in the FF 1b. 
Each of the decision edges EH and EL is a pulse having a period equal to that of the waveform switchover edge supplied from the timing generation circuit 41 to the test waveform generation circuit 43. The decision edges EH and EL are supplied to the logical value storage circuit 1 with a delay after the waveform switchover edge. The delay is equal to a time length between the waveform switchover edge and supply of the two-valued signals HCMP and LCMP to the logical value storage circuit 1 conducted in response to the test waveform output from the test waveform generation circuit 43. The delay is, for example, 10 nsec. Furthermore, since the response signal REP has a rise characteristic and a fall characteristic as shown in FIG. 10, there is a time discrepancy between the rise timing of the two-valued signal HCMP and the fall timing of the two-valued signal LCMP, and there is a time discrepancy between the fall timing of the two-valued signal HCMP and the rise timing of the two-valued signal LCMP. According to the time discrepancy, deskewing for setting a phase relation between the decision edges EH and EL is conducted by using a delay circuit (not illustrated). Furthermore, the decision edge EH is deskewed so as to become in timing either the rise interval or the fall interval during which the level of the two-valued signal HCMP changes. In the same way, the decision edge EL is deskewed so as to become in timing either the fall interval or the rise interval during which the level of the two-valued signal LCMP changes.
Referring back to FIG. 9, logical values of the two-valued signals HCMP and LCMP stored in the logical value storage circuit 1 are supplied to the expected value comparison circuit 5, and compared with expected values supplied from the pattern generation circuit 42. A result of comparison indicating whether they are coincident with each other is obtained. On the basis of the comparison result, it is determined whether the LSI 3 to be tested is fail or pass as the test result of the LSI 3 to be tested. The expected values output from the pattern generation circuit 42 are based on the waveform data supplied from the pattern generation circuit 42 to the test waveform generation circuit 43. Generation timing of the expected values is delayed from the waveform data by a time length between generation of the waveform data and supply of logical values to the expected value comparison circuit 5.
If the logical value storage circuit 1 samples the two-valued signals HCMP and LCMP by using the FF 1a and 1b and stores the logical value as described above, the following problems occur.
As a first problem, there is a problem that a difference occurs in the rise characteristic and the fall characteristic of the two-valued signals HCMP and LCMP obtained by the processing of the analog comparators 2a and 2b and consequently an error occurs in the decision of the test result. This problem will now be described with reference to FIG. 12. Although the problem will be described with respect to the two-valued signal HCMP, a similar problem occurs in the two-valued signal LCMP as well.
As shown in FIG. 12, the two-valued signal HCMP input to the FF 1a rises steeply and falls gently. In other words, there is a difference between the rise time and the fall time (transition times) of the waveform. It is now supposed that the FF 1a has a threshold of Vth. When a level of the two-valued signal HCMP lower than the threshold Vth is sampled at the decision edge EH, the logical value of the L level is stored in the FF 1a. When a level of the two-valued signal HCMP that is equal to or higher than the threshold Vth is sampled at the decision edge EH, the logical value of the H level is stored in the FF 1a. 
A rise interval of the two-valued HCMP is shown in FIG. 12. It is supposed that the rise is started at t0. It is also supposed that the phase of the decision edge EH is gradually changed from an illustrated position (1) of the two-valued signal HCMP to an illustrated position (2) in a direction indicated by an arrow. When the phase of the decision edge EH arrives at timing when the two-valued signal HCMP becomes the level of the threshold Vth in the rise interval, the logical value of the H level is stored in the FF 1a. If a Q output of the FF 1a has been at the L level, then the Q output rises at the timing and becomes the H level. The phase of the decision edge EH at this time is delayed from the rise start time point t0 by xcex94t. This phase of the decision edge EH is timing determined by taking the delay of 10 nsec into consideration. In this way, the decision edge EH is deskewed.
A fall interval of the two-valued HCMP is shown in FIG. 12. It is supposed that the fall is started at t0. If the decision edge EH is deskewed to timing delayed from the fall start time point t0 by the time length xcex94t in the same way as FIG. 12, and the fall time of the two-valued HCMP is equal to its rise time as represented by a broken line, then the Q output of the FF 1a is changed from the H level to the L level at a time point (t0+xcex94t) when the two-valued signal HCMP becomes a level equal to the threshold Vth. As a matter of fact, however, the fall of the two-valued signal HCMP becomes gentler than the rise as represented by a solid line. At a time point delayed from the fall time point t0 by xcex94t and a time tdiff ( greater than xcex94t), therefore, the level of the two-valued signal HCMP arrives at the threshold Vth. If the phase of the decision edge exists at the time point, the Q output of the FF 1a is changed from the H level to the L level at the time point.
Even if the sample timing of the two-valued signal HCMP caused by the decision edge EH exists in the rise time of the two-valued signal HCMP at a certain time point, the sample timing might in the fall time at another time point. If the phase of the decision edge EH is deskewed so as to become a time point (t0+xcex94t described above) delayed from the start time point of each of the rise time and the fall time of the two-valued signal HCMP by a fixed time, then a false logical value is stored in the FF 1a for the above described reason.
A second problem of the conventional logical value storage circuit 1 will now be described. If CMOS FFs (flip-flop circuits) are used as the FF 1a and FF 1b included in the logical value storage circuit 1, there occurs a difference in stored logical values because of a set up time difference between the FF 1a and FF 1b. And the time difference becomes an error caused at the time of storage. This is the second problem. This will now be described with reference to FIG. 13. In order to make the second problem clear, it is now supposed that the rise time of the two-valued signal HCMP is equal to the fall time thereof.
First, the rise of the two-valued signal HCMP will now be described. With reference to FIG. 13, it is supposed that the phase of the decision edge EH is gradually changed from an illustrated position (1) of the two-valued signal HCMP to an illustrated position (2) in a direction indicated by an arrow. When the phase of the decision edge EH arrives at a time point t0 when the level of the two-valued signal HCMP becomes the threshold Vth of the FF 1a, the Q output of the FF 1a is changed from the L level to the H level.
The fall of the two-valued signal HCMP will now be described. With reference to FIG. 13, it is supposed that the phase of the decision edge EH is gradually changed from an illustrated position (1) of the two-valued signal HCMP to an illustrated position (2) in a direction indicated by an arrow. Even if the phase of decision edge EH exists at a time point t0 when the level of the two-valued signal HCMP becomes the threshold Vth of the FF 1a, the Q output of the FF 1a is not changed from the H level to the L level. The Q output of the FF 1a is inverted in level only when the phase is delayed from t0 by tdiff.
Even if the rise characteristic of the two-valued signal HCMP is the same as the fall characteristic thereof, the phase of the decision edge EH measured from the time point t0 when the level inversion of the Q output is caused in the rise differs from that in the fall. (The difference is referred to as set up time difference.) As a result, an error is caused in a result of the logical decision. For example, in the case of the decision edge EH deskewed to the rise of the two-valued signal HCMP, a false decision is effected in the fall, even if the level (logical value) is judged correctly in the rise of the two-valued signal.
The second problem is such a set up time difference of the FF. Herein, however, the phenomenon that a logical value stored in the FF differs according to the immediately preceding stored value is referred to as set up time difference of FF.
An object of the present invention is to provide a high accuracy test apparatus capable of solving such problems and preventing an error from being caused in stored logical values by a difference between the rise characteristic and fall characteristic of a two-valued signal obtained from an analog comparator and the set up time difference of FF.
In order to acheve the object, in accordance with a first aspect of the present invention, a test apparatus includes, a comparator for comparing a response signal supplied from a device to be tested in response to a test waveform with a predetermined threshold and outputting a two-valued decision subject signal depending on a level of the response signal, timing generation means for generating a decision edge at predetermined timing for the decision subject signal, logical value storage means for extracting and storing logical values of the decision subject signal based on the decision edge, and comparison means for comparing an output of the logical value storage means with an expected value and determining whether the device to be tested should fail or pass. In the test apparatus, the logical value storage means includes first delay means for delaying the decision edge generated by the timing generation means by a predetermined time and generating a first decision edge, second delay means for delaying the decision edge generated by the timing generation means by a predetermined time and generating a second decision edge, the second decision edge being adjusted in timing with respect to the first decision edge according to a fall time of the decision subject signal, first storage means for storing a logical value of the decision subject signal obtained at timing of the first decision edge, second storage means for storing a logical value of the decision subject signal obtained at timing of the second decision edge, and selection means for selecting either the logical value stored in the first storage means or the logical value stored in the second storage means and supplying the selected logical value to the comparison means. When the first decision edge is in or near a fall time of the decision subject signal, the selection means selects the logical value stored in the second storage means.
In accordance with a second aspect of the present invention, in the test apparatus according to the first aspect of the present invention, the logical value storage means further includes third delay means for delaying the input decision subject signal by a predetermined time to generate a delayed decision subject signal, third storage means for storing a logical value of the delayed decision subject signal obtained at timing of the first decision edge, fourth storage means for storing a logical value of the delayed decision subject signal obtained at timing of the second decision edge, and means for controlling selection operation of the selection means based on a relation between the logical values stored in the third and fourth storage means.
In accordance with a third aspect of the present invention, a test apparatus includes a comparator for comparing a response signal supplied from a device to be tested in response to a test waveform with a predetermined threshold and outputting a two-valued decision subject signal depending on a level of the response signal, timing generation means for generating a decision edge at predetermined timing for the decision subject signal, first logical value storage means for extracting and storing logical values of the decision subject signal based on every other edge of the decision edge, second logical value storage means for extracting and storing logical values of the decision subject signal based on every other edge of the decision edge different from that for the first logical value storage means, first selection means for selecting the logical value stored in the first logical value storage means when the decision edge is supplied to the first logical value storage means and selecting the logical value stored in the second logical value storage means when the decision edge is supplied to the second logical value storage means, and comparison means for comparing an output of the first logical value storage means with an expected value and determining whether the device to be tested should fail or pass. Each of the first and second logical value storage means includes first delay means for delaying the decision edge generated by the timing generation means by a predetermined time and generating a first decision edge, second delay means for delaying the decision edge generated by the timing generation means by a predetermined time and generating a second decision edge, the second decision edge being adjusted in timing with respect to the first decision edge according to a fall time of the decision subject signal, first storage means for storing a logical value of the decision subject signal obtained at timing of the first decision edge, second storage means for storing a logical value of the decision subject signal obtained at timing of the second decision edge, second selection means for selecting either the logical value stored in the first storage means or the logical value stored in the second storage means and supplying the selected logical value to the first selection means, and reset means for resetting the first and second storage means at least before newly storing logical values of the decision subject signal at the first and second decision edges. When the first decision edge is in or near a fall time of the decision subject signal, the second selection means selects the logical value stored in the second storage means.
In accordance with a fourth aspect of the present invention, in the test apparatus according to the third aspect of the present invention, each of the first and second logical value storage means further includes third delay means for delaying the input decision subject signal by a predetermined time to generate a delayed decision subject signal, third storage means for storing a logical value of the delayed decision subject signal obtained at timing of the first decision edge; fourth storage means for storing a logical value of the delayed decision subject signal obtained at timing of the second decision edge, and means for controlling selection operation of the second selection means based on a relation between the logical values stored in the third and fourth storage means. The third and fourth storage means are also reset by the reset means at least before newly storing logical values of the delayed decision subject signal at the first and second decision edges.
In accordance with a fifth aspect of the present invention, in the test apparatus according to the fourth aspect of the present invention, the reset means resets the first to fourth storage means of the first logical value storage means at timing of the first decision edge in the second logical value storage means, and the reset means resets the first to fourth storage means of the second logical value storage means at timing of the second decision edge in the first logical value storage means.
In accordance with a sixth aspect of the present invention, a test apparatus includes a comparator for comparing a response signal supplied from a device to be tested in response to a test waveform with a predetermined threshold and outputting a two-valued decision subject signal depending on a level of the response signal, timing generation means for generating a decision edge at predetermined timing for the decision subject signal, logical value storage means for extracting and storing logical values of the decision subject signal based on the decision edge, and comparison means for comparing an output of the logical value storage means with an expected value and determining whether the device to be tested should fail or pass. The logical value storage means includes first delay means for delaying the decision edge generated by the timing generation means by a predetermined time and generating a first decision edge, second delay means for delaying the decision edge generated by the timing generation means by a predetermined time and generating a second decision edge, the second decision edge being adjusted in timing with respect to the first decision edge according to a fall time of the decision subject signal, first storage means for storing a logical value of the decision subject signal obtained at timing of the first decision edge, second storage means for storing a logical value of the decision subject signal obtained at timing of the second decision edge, and selection means for selecting either the logical value stored in the first storage means or the logical value stored in the second storage means and supplying the selected logical value to the comparison means, third storage means to which the logical value stored in the first storage means is transferred, fourth storage means to which the logical value stored in the second storage means is transferred, selection means for selecting either the logical value stored in the third storage means or the logical value stored in the fourth storage means, and supplying the selected logical value to the comparison means, and reset means for resetting the first and second storage means after the logical values have been transferred therefrom to the third and fourth storage means. When the first decision edge is in or near a fall time of the decision subject signal, the selection means selects the logical value stored in the fourth storage means.
In accordance with a seventh aspect of the present invention, in the test apparatus according to the sixth aspect of the present invention, the logical value storage means further includes third delay means for delaying the input decision subject signal by a predetermined time to generate a delayed decision subject signal, fifth storage means for storing a logical value of the delayed decision subject signal obtained at timing of the first decision edge, sixth storage means for storing a logical value of the delayed decision subject signal obtained at timing of the second decision edge, and seventh storage means to which the logical value stored in the fifth storage means is transferred, eighth storage means to which the logical value stored in the sixth storage means is transferred, and means for controlling selection operation of the selection means based on a relation between the logical values stored in the seventh and eighth storage means. The fifth and sixth storage means are also reset by the reset means after the logical values stored therein have been transferred to the seventh and eighth storage means.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.